A dual damascene process whereby both an interconnect groove and a via hole are formed in an interlayer dielectric, and subsequently, multi-level interconnects are formed by concurrently embedding a metal film in the interconnect groove, and the via hole, respectively, the dual damascene process has an advantage in that manufacturing cost can be considerably reduced because of reduction in the number of steps of processing. The dual damascene process includes a process shown in, for example, JP-A No. 11 (1999)-345875, JP-A No. 2004-140151, and JP-A No. 2007-081284, respectively, by way of example. With the process, an etching stopper film between interconnect layers in a region for a via is first worked on to thereby form an insulating film between the interconnect layers, and subsequently, an interlayer dielectric is etched, thereby concurrently forming an interconnect groove and a via hole.